The advantages of digital processing of an analog signal are well known. There arises a need for an analog-to-digital converter (hereinafter referred to as an ADC) responsive to higher sampling frequencies, or high speed ADC's for digitizing analog signals of increasingly higher frequencies. However, development of high speed ADC's satisfying the necessary requirements is attendant with technical difficulties. One conventional technique to alleviate this problem is to use a plurality of ADC's in parallel. A clock signal of different phases is applied to each of the parallel ADC's to digitize the input signal at different times so that the digitized outputs may be arranged sequentially in time to provide a high equivalent sampling frequency. In practice, however, phase shift errors and errors due to differences in propagation delay time have resulted in measurement inaccuracies.